Data processing system and method for accessing a common data memory

ABSTRACT

The present invention relates to a system and a method for data processing and a communications system controlled by such a system. The system comprises at least one central processor, a number of different function blocks and a common data memory (DS), At least one function is table executed in parallel with program execution by an execution processor (IPU) wherein the data memory (DS) either is used for program execution or for table execution wherein one or the other type of the execution has precedence and is able to interrupt an on-going execution of the other type.

TECHNICAL FIELD

The present invention relates to a system and a method respectively forprocessing of data. The invention in particular relates to such a systemfor controlling for example real-time systems wherein the requirementson execution efficiency etc. are high since various high-capacitydemanding functions have to meet real-time demands etc. In for examplecentrally controlled real-time systems of different kinds the systemcapacity for carrying out assigned functions is given by the executionefficiency of the central processor system.

The invention also relates to a communications system with such a systemfor data processing.

STATE OF THE ART

Numerous alternatives are known through which is intended to increasethe efficiency in a system for a processing of data, for example usedfor real-time controlling or in general for systems wherein therequirements are high as to execution efficiency due to various capacityrequiring functions. In order to achieve an increased efficiency it isamong others known to provide such a system architecture that it enablesa sharing of the total system load between different processors in theform of load and function sharing respectively. By so calledpre-processing given regional control functions are carried out usingregional processors and regional memories arranged in associatedfunction blocks. A central processor then commands the execution of thefunctions and receives the results thereof.

The regional processors and the central processor each control theirspecified function handling. Thus a system is obtained which has aconstant control load distribution. Such a system is in principle aone-processor system wherein the central processor controls functionblocks comprising regional processors. In such a system theinterprocessor-cooperation between the function blocks and the centralprocessor must be well defined by the latter. Another known system forload sharing generally denoted multiprocessing comprises at least twocentral processors. These together access the data memories of theestablishment and different computer configurations and control loaddistributions can be obtained for different operational periods. Throughthis processor redundancy a dynamical adaption to instantaneous traffichandling situations is enabled.

For both these kinds of systems interprocessor communication andprocessor cooperation is required which results in loads on the systemsetc.

One known way of increasing the efficiency of a centrally controlledreal-time system in which the system capacity is given by the executionefficiency of the central computer system is to execute in parallelexecutions through table controlled execution.

A highly demanding real-time system is for example a telecommunicationssystem.

In U.S. Pat. No. 3,969,701 table execution is applied. Variablesassociated with a function block are translated with the use of tablesfrom variable number to memory pointer values or address numbers in thememory operations in storing arrangements belonging to the respectiveblock.

In U.S. Pat. No. 4,354,231 the use of tables is described. In this casecache-memories are used which actually can be seen as fast memories. Inprinciple this only results in minor time savings and it is in no waypossible to obtain the increase in efficiency which is desired incentrally controlled real-time systems.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a system and a methodrespectively for processing of data wherein table control execution isused and through which a high efficiency can be achieved. Particularlyit is an object of the invention to provide a system for controllingcentrally controlled real-time systems in which a very high executionefficiency can be achieved.

One particular object of the present invention is to provide a systemthrough which the system capacity of a function block oriented centralprocessor system can be increased through the use of parallel executionsof functions with the use of table execution.

It is a particular object to provide a system in which descriptivefunction tables can be used for increasing the efficiency of for exampletelephony traffic handling on a functional level in the data processingsystem.

Furthermore it is a particular object of the invention to provide a hightotal-processor capacity.

Furthermore, according to a particular object of the invention it isintended to provide a high traffic handling capacity in a simple andefficient way as compared to what is hither to known.

Particularly it is also an object of the present invention to provide amethod through which the abovementioned objects are achieved. A furtherparticular object of the invention is to provide a telecommunicationssystem which is controlled by a system as referred to above.

These as well as further objects are achieved through a system for dataprocessing and a method for data processing respectively in which atleast one central processor is provided in which at least one functionis table-executed parallelly with program execution by a least oneexecution processor. According to the invention is particularly a hightotal processor capacity achieved through parallel execution offunctions in combination with one or more program executing processors.The combinations are given, according to a particular embodiment, takingload and function sharing aspects into account or in any other knownway. Those data variables which are necessary for the intended function,for example teletraffic control in the case of a telecommunicationsnetwork, can be executed in parallel in an efficient way through tablecontrolled execution. According to particular embodiments of theinvention such functions may for example be initiation of variables ordata posts, statistic information, data collection, data output etc.

According to a particular embodiment the invention can be used forinitiation of variable posts with a copying function which can be seenas a buffered job before the variable posts in an active way take partin the controlling of for example telephony switching. Particularly theinitiation can take place in connection with a clearing of theconnection. Variables which are to be initiated are in general allocatedin the data processing system and can be spread throughout the addressarea of the data storage. Therefor the logical address of the datavariables in the system are given. When accessing the memoryparticularly an address calculation is done to provide a physicaladdress from a logical address with the use of a reference table, whichis known per se. The logical addressing is a condition for theenablement of extending functions or providing changes in the datasystem during operation.

Particularly the variables can be of different format and they can beaddressed as individuals with pointer and/or index values.Advantageously a number of variables can be associated with each datarecord.

According to an advantageous embodiment relating to data initiationsetting with a copying function, first an executing table a so calledmasterpost is formed, one table per individual-variable record, whichgives variables to be given an initial value in the common data memoryand also the relevant values. For each variable is then one row providedin the table which comprises the logical address of the variable and aconstant. Particularly a logical address can be indexed and/or refer toa sub-variable the length of which may vary between for example 1 and128 bits. According to another advantageous embodiment the table maycomprise a loop forming instruction for initiation data setting forexample for indexed variables with the same logical address. The lengthof the table, i.e. the number of variables, can for example be given inthe first table word. According to an alternative embodiment the numberof variables or the table length can be given as the last data of thetable. The execution tables can as referred to above be formed forexample by the operation program of the data processing system at systemre-starts or at start up. A program executing processor with a programinstruction intended therefor activates masterposts for execution of thecontent of the tables.

With the use of this program instruction table execution in the programexecuting processor is carried out in parallel with a running trafficcontrol program. According to an advantageous embodiment the tableexecution is terminated by a synchronization activity towards aprocessor for example by setting a so called state-bit to confirm that ajob is terminated. According to an alternative embodiment programsynchronization can be achieved through sending a signal to the programexecuting processor. The state-bit or the state-bits can then besearched using a searching instruction in the processor through whichthe processor is provided with information of which variable recordswhich are resources that are available for the traffic controllingprocess.

The table executions are adapted to the system and it does not relate toany program control but every line of the table is particularly directobject controlling without the participation of any programadministration instructions.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will in the following be further described in anon-limiting way under reference to the accompanying drawings in which:

FIG. 1 illustrates a data processing system and

FIG. 2 illustrates an example of an internal structure 6 a tableexecution unit.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates one example of connection of a table executing unitDVX in a data processing system and internal communication betweendifferent units of the data processing system. In the schematicalillustration of the data processing system, apart from the tableexecuting unit DVX, two processor units or execution processors IPU₁ andIPU₂ are provided. These are connected to a centrally controlled bussand access handler ACC (Address Calculation Circuit). In the shownembodiment there are two execution processors IPU₁, IPU₂. This is ofcourse only an example; according to another embodiment the systemcomprises only one executing processor and according to still furtherembodiments the system comprises more than two parallel executionprocessors or processor units. Each processor unit or executionprocessor comprises a program memory PS. Furthermore the systemcomprises a common data memory DS and the table executing unit DVX andthe connection of the processing units IPU₁, IPU₂ to aninter-communication system which however will not be more thoroughlydisclosed here since this in a manner which is known per se provides forcommunication with other systems etc.

The table executing unit DVX and the program execution processor(s)IPU₁, IPU₂ are connected between the intercommunication system and thesystem common memory DS for variables.

According to an advantageous embodiment the table executing unit DVXsupports, when needed, efficient data transferring between the dataprocessing system and various peripheral units in a way which is knownper se using direct memory access (DMA-channel access) to the commondata memory DS.

The common data memory DS can be organized in different ways. Accordingto an advantageous embodiment the common data memory uses anorganization of the memory which applies so called inter-leaving in amanner which is known per se and it operates in a multiplexing so calledpipe-line structure towards free memory banks. These free memory banksin principle behave like fast memories. An address calculation circuitACC controls the assignment of buss and memory accesses in themultiplexed data storage.

In FIG. 2 an example on an internal structure of a table executing unitDVX is illustrated. (One of its functions may e.g. relate to givinginitial values to fullword variables in the data memory. Fullwordvariable means the directly controllable data format in the memory forwrite in without preceding read out of the memory word.)

Irrespective of the origin of an initiation, all memory accesses are inthe shown embodiment done via the address calculation circuit which alsocontrols the current order or sequential order. A calling unit and acalled memory bank in most cases cooperate in an asynchronous way.Synchronizing is done by the address calculation circuit ACC, forexample according to an advantageous embodiment in that it indicateswhen a memory address and write data respectively may occupy the bussfor the memory access itself. For example a ready-bit (synchronization)can be used to indicate that read data is available whereas if theready-bit is not shown, there is a waiting position.

The tables comprise a table setting for each initiation, control thejobs intended for the table executing unit which (the table executingunit DVX) independently executes these jobs. The variable accesses arerequested via the address calculation circuit ACC and advantageouslythis comprises a priority order for handling the variable-accesses. Theasynchronous coordination and an efficient pipe-line structure howeverrequire intermediate buffers for memory addresses and write data or insome cases read data. The table executing unit DVX comprises buffermemories for the register of the data processing system for logicaladdressing of variables, Base Start Address BSA₁, BSA₂ and PRS₁, PRS₂.BSA gives the address of a base table associated with a function blockwhereas PRS gives the individual number, i.e. the pointer to thevariable record. These registers are set by the processor initiating thestart of the table execution with an instruction WCX of the programintended therefor. There is also a register for WCX. WCX brings anexecution table pointer MP₁, MP₂ (see FIG. 2) which is an address of thetable to be executed. According to an advantageous embodiment the tablesare so arranged that they form a fast memory. In the illustratedembodiment the first row of the table contains information about thenumber of variables or rows in the table which are affected by thecopying whereas on the next row follows the first variable having alogical address "a" and the value of the constant to be set as aninitial value, usually 0 or 1. On the following row the next variable isgiven etc. up to the last row of the table which is used for setting aso called state-bit with logical address "a". In the figure the n:thexecution table is merely schematically indicated wherein n gives thenumber of execution tables of the system; there may be one or more. WCXstarts the execution process and activates the control logic foraddressing of the execution table which shall read the number of thevariables and a so called loop-counter COUNT is loaded for the controllogic. In the table is stepped by +1 to the next row and the firstvariable of the table. The logical address part (a) together with a BaseStart Address, the BSA-content provides via an addressing circuit ADD anaddress to that reference table from which the physical data position ofthe memory is obtained (not shown). The memory address of the variableis given by calculation of WA, i.e. the physical data position in thememory and the pointer value in PRS (offset). In the present case anindex value is also obtained. The address calculation itself iscontrolled via the above mentioned pipe-line stage and the constant partis transferred to the write data buffer. In the last pipeline stages ofthe address calculation a request for a memory access to the addresscalculation circuit ACC is activated according to the calculatedvariable address. Then, according to an advantageous embodiment, theinitial constant is written in the common data memory DS. Tablecalculation is

for example discussed in SE-B-439.208.

The WCX queue is according to an advantageous embodiment, handledsequentially and information about "full buffer" is given to theexecution processor IPU or, if applicable, the concerned processor unit.Dashed lines in the - figure denote among others extensions when avariable is to be read and handled internally before re-writing in thecommon data memory DS. The pipe-line controlling as referred above maysometimes be stopped temporarily depending on the controllingparticipation of the address calculation circuit when memory accessesare executed. Normally, however, the table execution is terminated withthe last row of the table when, according to advantageous embodiment,the state-bit is set in the data memory DS or through sending of asignal. According to an advantageous embodiment program execution by anexecution processor IPU has preference over table execution through thetable executing unit DVX. The parallel execution is then so applied thatwhen the memory DS is free, i.e. not used by the execution processor forprogram execution, e.g. for traffic control or anything else, it is usedfor table execution. When the execution processor IPU again needs to usethe data memory DS, it can interrupt a table execution in progress.

Of course the data processing system according to the invention can beused in other systems than telecommunications systems. Also in otheraspects the invention is not limited to the shown embodiments but it canbe varied in a number of ways within the scope of the claims.

We claim:
 1. A system for processing data comprising:a central processorsystem wherein a number of function blocks are assigned given functions,comprising at least one program execution processor and a data memory,wherein the system comprises at least one table execution unit whichcomprises at least one execution table and in that a number of variablesare allocated in the data memory and in that program execution by atleast one execution processor is done in parallel with table executionby the table execution unit wherein either program execution or tableexecution has prioritized access to the data memory and can interrupt anon-going execution of the other kind so that the data memory from a timeaspect is used either for program execution or table execution.
 2. Thesystem according to claim 1, wherein program execution by the executionprocessors has a higher priority than table execution by the executionunit which uses the data memory when this is not used for programexecution.
 3. The system according to claim 2, wherein on-going tableexecution can be interrupted for program execution by the executionprocessor.
 4. The system according to claim 1, wherein the function ofgiving variables or data records initial values with a copying functionis executed in parallel with execution of traffic control programs bythe program execution unit.
 5. The system according to claim 4, whereinthe collection of statistical information is a table executed function.6. The system according to claim 1, wherein the functions datacollection and/or data output is/are table executed.
 7. The systemaccording to claim 1, wherein variables are addressed as individualse.g. with pointer values and/or index values.
 8. The system according toclaim 7, wherein one or more variables are associated with an individualrecord.
 9. The system according to claim 4, wherein a table/individualvariable record, an execution table, is formed which at least gives thevariables to be given an initial value.
 10. The system according toclaim 9, wherein the execution table also provides the initial valueswhich are to be given to the variables.
 11. The system according toclaim 10, wherein the initiation-value is given in the execution table.12. The system according to claim 11, wherein each variable disposes onerow in the execution table which at least contains the logical addressof the variable and a constant.
 13. The system according to claim 12,wherein the logical address indicates a variable of arbitrary length.14. The system according to claim 9, wherein the execution tables areformed by an operating system of the data processing system.
 15. Thesystem according to claim 1, wherein program synchronization is providedby transmission of a signal to the concerned central processor orexecution processor or by confirmation of a terminated job e.g. througha state-bit or similar for informing about which variable records thatare resources which are free for the program execution or the trafficcontrolling process.
 16. The system according to claim 1, wherein everyrow of the table is directly object controlling.
 17. The systemaccording to claims 1, wherein it is used for controlling a computersystem.
 18. The system according to claim 16, wherein it is used forcontrolling a centrally controlled telecommunications system.
 19. Thesystem according to claim 18, wherein the centrally controlledtelecommunications system is the so called AXE-system.
 20. Acommunications system comprising:at least one system for data processingwhich at least comprises one execution processor and at least one datamemory that is accessible by the execution processor, wherein: the dataprocessing system comprises at least one table execution unit thatcomprises an execution table and is capable of accessing the datamemory; a number of data variables are allocated in the data memory; andtable execution of at least one variable is done in parallel withexecution of traffic controlling programs by an execution processor,wherein the execution is done in such a way that an on-going tableexecution is interrupted by the execution processor for trafficcontrolling if the execution processor needs access to the data memory.21. A method for processing data in a system including a number offunction units, at least one execution processor and a data memory, themethod comprising the steps such that:execution is done by the executionprocessor in parallel with execution by a table execution unit thatfunction tables are used for controlling those functions that are to beexecuted in parallel with execution by the execution processor whereinthe table execution unit is connected to a data memory which is commonfor the system and wherein table execution is done when the data memoryis not used by the execution processor for program execution.